Via Filled and Via in Pad

Via Filling is a Technique that Guarantees Completely Closed Via Holes.

This can be Via Filling with Resin or with Soldermask.

Via hole, also known as a conductive hole, plays the role of connecting lines to each other.

With the development of electronic products in the direction of “lighter, thinner and smaller”, PCBs have also developed to high density and high difficulty.

Therefore, a large number of SMT and BGA PCBs have appeared, and the plugging process has been produced.

What is Via in Pad

With the development of electronic products and applications of finer pitch devices, vias play an important role in the interconnection between layers in a PCB。

There are three main types of vias: through-hole vias, blind vias and buried vias, each of them has different attributes and functions contributing to the overall optimal performance of circuit boards or even electronic products.

However, via in pad have been widely used in small-scale PCBs and BGA.

With the necessity of high-density BGAs (ball grid arrays) and the miniaturization of SMD chips, the use of via-in-pad technology is increasingly important.

Via in Pad

What is Via Plugging

Via plugging is a process in which vias are completely filled with resin or closed with a solder mask.

This technique is different from via tenting where resin/solder mask doesn’t fill the via hole but just provides a covering.

Via Plugging through Soldermask

Via plugging is done as a preventive measure to secure the vias from the unwanted flow of solder material during the assembly/soldering process.

During the soldering process, if a via is not plugged or tented, the solder can flow down the via from the pads and can create unnecessary solder joints.

Application of Soldermask Layer on a PCB after Plugging

Via plugging can be done through conductive or non-conductive material.

The conductively filled vias help to carry a large amount of current from one side of the PCB board to another.

However, the main drawback of conductively filled vias is the difference in CTE (Coefficient of Thermal Expansion) between the conductive fill and surrounding laminate.

During PCB operation, the conductive material will heat and expand at a faster rate than the surrounding laminate, which can cause a fracture between the via wall and associated contact pad.

The via holes filled with non-conductive materials will still function like normal vias.

However, they will not be able to carry higher current loads like those filled with conductive materials.

What Difference Via Plugging with Resin and Soldermask

the main difference is the fullness. In other aspects, such as acid and alkali resistance, resin plug holes have an advantage over green solder mask.

The process of using resin plug holes in PCB is often due to BGA components, because traditional BGA may make VIA between PAD and PAD to the back of the lines.

But if the BGA is too dense and the VIA cannot go out, you will make via and then directly drill from the PAD to another layer to route the lines.

Then the hole is filled with resin and copper-plated into PAD, which is commonly known as the VIP process (via in pad).

If you just make via on the PAD without plugging the hole with resin, it is easy to cause leakage of tin and lead to a short circuit on the back and front Empty welding.

The process of PCB resin plugging includes drilling, electroplating, plugging, baking, grinding, and drilling, then the holes are plated through, then the resin is plugged and baked, finally the resin is polished and smoothed, make sure there’s no copper.

Therefore, it needs to plate one copper layer to turn it into a PAD.

These processes are all done before the original PCB drilling process, all via plugging with resin and plating, then other holes are drilled, it will follow the standard process for this PCB.

In fact, the HDI board should have vias plugging with resin and plating.

Generally, the opening solder mask is the through-hole,in other words, the size of the PTH is more than 0.35mm, there should be no solder mask oil in the hole.

The via plugging with solder mask is mainly used for the plugging of the BGA multi-layer board in SMT production.

The NPTH hole with a diameter is less than 0.35mm.

The reason for the via plugging is to prevent this NPTH from being in the natural environment for many years, after being oxidized and corroded by acid and alkali, it will cause a short circuit and cause poor electrical properties, so plugging should be made.

The standard for BGA plugging is opaque, and it is best to fill up two-thirds of the hole.

It seems that some customers who have BGA require via plugging solder mask.

Parasitic Capacitance and Inductance of Vias

The via itself has parasitic stray capacitance. If it is known that the diameter of the solder mask on the ground layer of the via is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate Is ε, the parasitic capacitance of the via is approximate: C=1.41εTD1/(D2-D1)

The main effect of the parasitic capacitance of the via hole on the circuit is to extend the rise time of the signal and reduce the speed of the circuit.

For example, for a PCB board with a thickness of 50mil, if the diameter of the via pad is 20mil (the diameter of the hole is 10mils), and the diameter of the solder mask is 40mil, then we can approximate the size of the via using the above formula.

The parasitic capacitance is rough: C=1.41×4.4×0.050×0.020/(0.040-0.020)=0.31pF.

The rise time change caused by this part of the capacitance is rough: T10-90=2.2C(Z0/2)=2.2×0 .31x(50/2)=17.05ps .

It can be seen from these values ​​that although the effect of the rise delay caused by the parasitic capacitance of a single via is not obvious if the via is used multiple times in the trace for interlayer When switching, multiple vias will be used, which must be carefully considered during design.

In actual design, the parasitic capacitance can be reduced by increasing the distance between the via hole and the copper area (AnTI-pad) or reducing the diameter of the pad.

Parasitic capacitances exist in vias as well as parasitic inductances.

In the design of high-speed digital circuits, the harm caused by the parasitic inductances of vias is often greater than the impact of parasitic capacitance.

Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system.

We can use the following empirical formula to simply calculate the parasitic inductance of a via: L=5.08h [ln(4h/d)+1]

Where L refers to the inductance of the via, H is the length of the via, and D is the diameter of the center hole.

It can be seen from the formula that the diameter of the via has a small influence on the inductance, and the length of the via has the greatest influence on the inductance. Still using the above example, the inductance of the via can be calculated as:

L=5.08×0.050[ln(4×0.050/0.010)+1]=1.015nH

If the rise time of the signal is 1ns, then the equivalent impedance is XL=πL/T10-90=3.19Ω.

Such impedance can no longer be ignored when high-frequency current passes.

Special attention should be paid to the fact that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer so that the parasitic inductance of the via will double.

How to Use the Vias

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design.

In order to reduce the adverse effects caused by the parasitic effects of vias, the following can be done in the design:

1. Considering both cost and signal quality, choose a reasonable size via size. If necessary, you can consider using different sizes of vias. For example, for power or ground vias, you can consider using a larger size to reduce impedance, and for signal traces, you can use smaller vias. Of course, as the size of the via decreases, the corresponding cost will increase.
2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.
3. Try not to change the layers of the signal traces on the PCB board, that is, try not to use unnecessary vias.
4. The pins of the power supply and the ground should be drilled nearby, and the lead between the via and the pin should be as short as possible. Consider drilling multiple vias in parallel to reduce the equivalent inductance.
5. Place some grounded vias near the vias of the signal change layer to provide the closest return to the signal. You can even place a lot of redundant ground vias on the PCB. Of course, the design needs to be flexible. The via model discussed earlier is the case where there are pads on each layer. Sometimes, we can reduce or even remove the pads of some layers. Especially in the case of a very high density of vias, it may lead to the formation of a broken groove in the copper layer to isolate the circuit. To solve this problem, in addition to moving the position of the via, we can also consider placing the via on the copper layer. The pad size is reduced.
6. For high-speed PCB boards with higher density, you can consider using micro vias.